Low-Power Synthesis Technique with Dynamic Supply Gating
- 總結
- Purdue University researchers have developed a novel method to reduce switching power dissipating and subthreshold leakage current in CMOS integrated circuits.
- 技術優勢
- Dramatic power reduction without performance sacrificeExtends battery life of portable electronic devices Improves reliability of integrated circuitsIncreased scope of applications for nanometer technologies
- 技術應用
- CircuitryDevices
- 詳細技術說明
- Kaushik RoyNanoelectronics Research LaboratoryPurdue Electrical and Computer Engineering
- *Abstract
-
- *Background
- As electronics get smaller, the demand for smaller complementary metal oxide semiconductor (CMOS) devices increases. However, smaller CMOS devices produce undesired effects such as increased subthreshold leakage current. In the past, these problems have been offset by reducing the supply voltage, which results in significant degradation in performance.
- *IP Issue Date
- Nov 18, 2008
- *IP Type
- Utility
- *Stage of Development
- Prototype Testing in Economic Run
- *Web Links
- Purdue Office of Technology CommercializationPurdueInnovation and EntrepreneurshipKaushik RoyNanoelectronics Research LaboratoryElectrical and Computer Engineering
- 國家
- United States
- 申請號碼
- 7,454,738
- 國家/地區
- 美國
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