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Frequency and Phase Locked Loops

Summary

There are Jitter issues and long lock time issue with current Phase Locked Loop.

This pending patent is to analyse the root cause of the Jitter issues from design

theory to design implementation of current Phase Locked Loop and to provide

solutions to significantly remove most Jitters (long term jitter, cycle-to-cycle jitter

etc), to reduce lock time from 10 ms down to about 10 us level and to achieve

high static frequency and phase accuracy(better than 50ppm).

Technology Benefits

Any electronic device operating at high frequency bigger than 1GHz needs Phase locked loop such as cell phone or computer.

Coverage Areas

CANADA

Goods and Services

Sale, License agreement

Patent Information

patent application, not published

Others

The content of this pending patent application was published by EDN in Nov,2014.

http://www.edn.com/design/analog/4437244/Frequency-and-Phase-Locked-LoopsPLL-

Country/Region

Canada

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